library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity NZP_Logic is
    port(Clk: in bit;
         LD_CC: in bit;
         BUS_in:    in unsigned(15 downto 0);
         N, Z, P: out bit);
end entity NZP_Logic;

architecture build of NZP_Logic is
    begin
        process(Clk)
            begin
                if Clk = '1' and Clk'event then
                    if LD_CC = '1' then
                    if   BUS_in(15) = '1' then
                        N <= '1';
                        Z <= '0';
                        P <= '0';
                    elsif BUS_in = "0000000000000000" then
                        N <= '0';
                        Z <= '1';
                        P <= '0';
                    else
                        N <= '0';
                        Z <= '0';
                        P <= '1';
                    end if;
                    end if;
                end if;
            end process;
    end build;
